1. Field of the Invention
The present invention relates to improvements in gate driving circuits. More particularly, the invention relates to improvements particularly suited for providing gate driving circuits in a bi-hecto celcius (200 degrees celcius) operating environment having multiple functions including combinations of multiple level logic inputs, noise immunity, fault protection, overlap protection, pulse modulation, high-frequency modulation with transformer based isolation, high-frequency demodulation back to pulse width modulation, deadtime generator, level shifter for high side transistor, overcurrent protection, and undervoltage lockout. In particular, the present invention relates a single circuit providing all of this functionality in a compact robust package.
2. Description of the Known Art
As will be appreciated by those skilled in the art, half bridge gate drivers are known in various forms. Patents disclosing information relevant to bird guards include:
U.S. Pat. No. 6,556,053, issued to Stanley on Apr. 29, 2003 entitled Half-bridge gate driver optimized for hard-switching; U.S. Pat. No. 7,436,160, issued to Rusu, et al. on Oct. 14, 2008 entitled Half bridge adaptive dead time circuit and method; U.S. Pat. No. 7,688,049, issued to Iwabuchi, et al. on Mar. 30, 2010 entitled Level shift circuit and power supply device; and U.S. Pat. No. 7,965,522, issued to Hornberger, et al. on Jun. 21, 2011 entitled Low-loss noise-resistant high-temperature gate driver circuits. Each of these patents is hereby expressly incorporated by reference in their entirety.
U.S. Pat. No. 6,556,053, issued to Stanley on Apr. 29, 2003 entitled Half-bridge gate driver optimized for hard-switching discusses its abstract as follows: A half-bridge gate driver circuit including two separate floating high-side driver circuits for operating a switch circuit having a high-side switch and a low-side switch. Each of the driver circuits include input control logic which is referenced to a supply signal with a potential that becomes negative relative to the negative common terminal of the switches, thereby enhancing the operation of the switch circuit. The circuit may further include signal translation stages for translating control signals to the control logic of the driver circuits. The signal translation stages include a plurality of cascoded parasitic transistors which provide a neutralizing capacitance to minimize noise.
U.S. Pat. No. 7,436,160, issued to Rusu, et al. on Oct. 14, 2008 entitled Half bridge adaptive dead time circuit and method describes its abstract as follows: A high voltage offset detection circuit registers the voltage at the midpoint of a switching half-bridge and may determine when the midpoint voltage reaches a given value to avoid hard-switching in the half-bridge switches. The midpoint voltage of the switching half-bridge is applied through a buffer to a MOSFET that is current limited to produce a voltage that reflects the voltage of the midpoint of the switching half-bridge. The voltage produced by the MOSFET may be supplied to a comparator with a threshold input to obtain a signal that indicates when the switches of the switching half-bridge may be turned on to avoid hard-switching. An adaptive dead-time circuit and method may comprise the above sensing circuit, a first circuit for generating a first signal indicative of a high to low transition of the midpoint voltage; and an output circuit for generating an adaptive dead-time output signal based thereon. A second circuit may generate a second signal indicative of a low to high transition of the voltage; wherein the output circuit generates the adaptive dead-time output signal based on both the first and second signals. The second circuit preferably generates the second signal by reproducing the first signal. The first circuit may generate the first signal by charging a capacitor in response to pulses, and the second circuit may generate the second signal by charging a second capacitor corresponding to said first capacitor, and the adaptive dead-time output signal may be responsive to the charges on the first and second capacitors.
U.S. Pat. No. 7,688,049, issued to Iwabuchi, et al. on Mar. 30, 2010 entitled Level shift circuit and power supply device describes its abstract as: In a level shift circuit including: an inverter circuit having a series circuit of a Pch-type transistor and an Nch-type transistor, which re connected between electrodes of a floating power supply; and a transistor Q1 in which a drain terminal and a source terminal are connected between an input terminal of the inverter circuit and a ground, wherein a drain terminal and source terminal of a transistor Q2 are connected between one terminal of the floating power supply and the drain of the transistor Q1, and a drain terminal and source terminal of a transistor Q3 are connected between a control terminal of the transistor Q2 and the ground.
U.S. Pat. No. 7,965,522, issued to Hornberger, et al. on Jun. 21, 2011 entitled Low-loss noise-resistant high-temperature gate driver circuits describes its abstract as: High temperature gate driving circuits with improved noise resistance and minimized loss are implemented with high temperature components with a reduced size magnetic isolation transformer. Input broad-pulse width modulated signals are converted to offsetting narrow pulses to cross the reduced size magnetic transformer minimizing isolation losses. One embodiment teaches time and voltage offset narrow single pulses that control a set and reset regeneration of the pulse width output on the secondary side of the transformer. Another embodiment teaches multiple concurrent voltage offset pulses to cross the transformer and charge a threshold capacitor for both filtering noise and controlling the pulse width regeneration on the secondary side of the transformer.
From these prior references it may be seen that these prior art patents are very limited in their teaching and utilization, and an improved half bridge gate driver is needed to overcome these limitations.